As an Application Engineer you will have the exciting opportunity to work closely with customers supporting technical campaigns by delivering product demonstrations, knowledge transfer, training and onsite support. This will involve working with packaging of electronics using highly integrated IC package co-design and multi-die chiplet methodologies. The candidate should have knowledge of standard IC packaging methods including wirebond, flipchip , interposer technology and design implementation techniques supporting high speed technologies. Knowledge with the latest trends and the advancement of Heterogenous Integration applications is a plus.
The candidate needs the ability to address the following areas:
- Analyze a customer’s requirements and develop appropriate solutions.
- Be knowledgeable and aware of the competitive landscape.
- Anticipate technical issues and develop creative solutions before they become a problem.
- Able to communicate effectively with customers and Cadence R&D, Product Engineering, Marketing.
- Understand customer success criteria and be committed to ensuring customer success.
Requirements:
- Master’s degree in Electrical or Electronics Engineering with 7-10 years related industry experience
- Design or AE experience in IC packaging including but not limited to wire bond, flip chip and multi die implementation.
- Knowledge of both interposer design and heterogeneous integration technologies and applications is a plus.
- Working experience with IC physical implementation tools such as Cadence Virtuoso is a plus.
- Understanding of the industry with multi-platform design implementation across IC and IC Package integration.
- Knowledge of Cadence Allegro platform tools for IC packaging and PCB design.
- Excellent written and verbal communication skills are required. Ability to present and clearly articulate solutions individually and in front of medium to large groups is required.
