Job Description Summary:
Senior Technical field Application Engineer for Cadence Digital and Signoff Group (DSG) products. Support Cadence digital tools across the full RTL-GDSII Cadence digital tool suite
Job Description:
This senior role includes the following operations and requirements:
o Work with a customer as a product and flow specialist with deep technical knowledge in focus area of Synthesis, Placement, Routing, and timing closure but should also be familiar with RTL to GDSII design of integrated circuits.
o Develop an understanding of the customer’s needs for IC design and also of the competition’s technology and sales strategies.
o Assists sales staff in assessing potential application of company product to meet customer needs and applying the tools and flows.
o Amend and augment the flow using tcl and/or other programming skills.
o Participate in customer benchmark and pre-release activities
o Participate in customer visits and sales calls, both in discovery mode to identify needs/requirements and in actual product sales engagements
o Conduct technical presentations and product demonstrations to customers.
o Support technical evaluations/benchmarks and drive the process to deliver Cadence solutions implementations
o Build highly effective corporate relationships within R&D and Product Engineering to address product defects as well as drive customer requirements into next generation product
o Develop strong, positive customer support
o Instruct and teach customers on how to produce optimal quantitative and qualitative results
o work creativity and independently to deliver 100% customer satisfaction when provided with account objectives
o On-site customer support as needed
o Communicate with customers on issue workarounds and new tool fixes
o Mentor and lead less-experienced team members
Position Requirements:
· Broad knowledge and at least 8+ years of experience in the physical design process of modern SOCs (16nm or below)
· Demonstrated hands-on experiance and expertise in several of the following areas: RTL Synthesis/Physical Synthesis, Design constraint creation process for complex processors, IP or SOCs, Timing Optimization and Closure, Static timing analysis and Design Constraints, Power Analysis and Optimization (Dynamic, Leakage, EM), Low power implementation, Clock Tree Synthesis, Routing, CAD flow debug/optimization
· Proven track record of solving complex problem in physical design
·Strong skills at understanding customer needs and identifying solutions to their challenges with Cadence Backend Implementation Tools
·Willingness to learn new tasks and adapt to change, establish priorities and handle various tasks simultaneously, perform job under pressure or in critical situations
· Demonstrated ability in customer tool debug and usage issues (on-site and remote)
·Past direct experience with Cadence P&R & Synthesis, or other equivalent products
· Outstanding oral communication skills to deliver customer and marketing presentations, product updates, etc.
· Excellent TCL programming skills – Ability to take a customer spec and code solution in TCL
· BSEE/CE (MSEE/CE Preferred)