At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
1. Proficient in RTL coding, datapath designs, complex FIFO design
2. Strong knowledge on complete design flows and rigorous checks before delivery to other teams or customers ex- LINT, SDC, CDC, DFT, Low power and trial PnR
3. Good experience of micro architecture, design, synthesize for a complex SerDes IP in various technology nodes.
4. Desired Protocols knowledge – USB, PCie, MIPI(DPHY), HDMI/Display
5. Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits
6. Good understanding of working with signal processing IPs in terms of knowing calibrations, plls, dividers.
Nature of work:
Candidate will be responsible for the design and implementation of high speed serdes PHY at the cutting edge nodes.
Responsibilities includes architecture of high speed Serdes IP, design, lint, synthesis, static timing analysis, DFT, formal verification, at block, core, and chip levels.
Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits
Requirement:
Candidate is expected to have good understanding of design and implementation of complex algorithm.
Proficient in high speed design, RTL coding, datapath designs, complex FIFO design working at Ghz frequencies.
Good experience of micro architecture, design, synthesize for a complex SerDes IP in various technology nodes.
Strong knowledge on complete design flows and rigorous checks before delivery to customers ex- LINT, SDC, CDC, DFT, Low power and trial PnR
