Design Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As a member of the Design Verification Team for Xtensa processors you will be responsible for verification of microprocessor cores and their peripherals. Under the mentor-ship of a technical lead, you will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test plans, documenting diags, debugging failures and analyzing coverage information.

 

Required Skills and Experience:

 

2-3 years of design verification experience

BS (or higher) in EE/Computer Engineering

Knowledge of computer architecture and design verification fundamentals

Experience with Verilog and popular EDA simulation, SystemVerilog and testbench methodologies

Exposure to scripting languages like Perl, Unix shell or similar languages

Experience with assembly language programming required

Excellent written and oral communication skills necessary

Knowledge of vManager will be added advantage

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