Job Description
RFIC Design Engineer
You will be responsible for the development of RF LNA circuits on SOI CMOS processes that are used in front-end modules for wireless applications. Responsibilities include architecture study, circuit design, simulation, verification, and production ramp support of highly integrated, high volume RFICs for high-growth, fast-paced, and competitive wireless handset market. Knowledge of PA, switch, filter and module design wireless systems is a plus. Familiarity with cellular standards will be useful. You must be able to work well with other design engineers, system engineers and CAD layout designers. You will face challenging tasks in order to meet critical performance parameters in the design of state-of-the-art LNAs. Very good understanding of semiconductor physics and strong circuit simulation skills utilizing Cadence is necessary. You are expected to lead complex LNA designs. #LI-DB1
The Mobile Solutions (MS) team at Skyworks develops industry-leading, highly integrated solutions for next generation mobile platforms supporting the world’s leading smartphone manufacturers. Our design engineers have diverse expertise and utilize a broad range of technologies (SOI, silicon CMOS, GaAs, IPD, TC-SAW and pHEMT) to create differentiated transmit and receive products including high performance LNAs, couplers, power amplifiers, antenna switch modules, digital/analog controllers, passive matching and acoustic filtering for leading edge 3GPP standards. Skyworks’ MSB team is an ideal place for motivated engineers who enjoy collaboration in a fast-paced environment and designing industry breakthrough solutions for mobile and 5G applications.
Job Requirements:
•BSEE + 8 years, or MSEE + 6 years or PhD + 3 years of working experience.
•Demonstrated RFIC design experience using SOI CMOS
•Understanding of associated analog control and bias circuits
•Experienced in implementing on-chip ESD protection strategies for HBM/MM/CDM on RFIC
•Strong understanding of silicon fabrication and how it affects the device physics, device model, and circuit performance
•Strong understanding and practical expertise of both on-die and in-package coupling mechanisms is required, including modeling and simulation using EM simulations at the die and package level
•Demonstrated experience debugging, resolving and applying techniques to mitigate analog/RF/mixed signal noise issues and RF coupling, shielding, and grounding
•Proficient with Cadence Spectre (RF), GoldenGate, BDA and ADS simulation tools (Sparameter, HB, envelope)
•Experience with EM simulation tools such as HFSS and EMX
•Strong understanding of packaging techniques such as wire bonding (single chip and multi-chip packages) and flip-chip technologies for RF products and their impacts on design
•Experience with Smith chart, load and source pulling, RF matching, transmission lines in both simulation and lab environment
•Layout experience using the Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on RF and analog layouts
•Knowledgeable of all RF parameters such as stability, return loss, harmonics, IMD, P1dB, NF, switching speed, IIP2/3, and ability to design and optimize for each parameter
•Strong hands on experience of lab equipment including RF signal generators, oscilloscopes, power amplifiers, filters, duplexers, diplexers, spectrum analyzer, power sensors, and VNAs is required
