Cadence Design

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description : Be part of the Cadence DDR PHY IP development team responsible for – -Defining microarchitecture of digital blocks to meet specifications, ensuring modularity , optimized for performance metrics of timing, area and power. -Lead

Job Description: R&D Applications Engineer – DSP The Applications Engineer is responsible for working directly with Cadence Tensilica customers to provide technical support, application know how and training on Tensilica products. You will also interact with Tensilica sales and field application engineering teams, other members of the Applications Engineering team as well as the development engineering team to support the

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 1. Proficient in RTL coding, datapath designs, complex FIFO design 2. Strong knowledge on complete design flows and rigorous checks before delivery to other teams or customers ex- LINT, SDC, CDC, DFT, Low power and trial PnR 3. Good experience

BANGALORE At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Principal Education AE: At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. As an integral part of the Cadence Education Services Team, you will create and

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Strong C/C++ development skills with a good understanding of object-oriented design. Strong background of computer science fundamentals (data structures, algorithms) Passion to learn / explore new technologies and demonstrates good problem-solving skills. Experience of EDA tool development and static timing

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Design Verification expert with good subsystem and IP level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Independently handle verification of subsystem/IP. Define methodology for subsystem/IP verification. Follow systematic approach of metric driven verification