Cadence Design

Technical PreSales AE working with Cadence Analog Layout tools, including Cadence Design Framework (DFII), schematic capture (VSE) and Virtuoso layout (VLS). Minimum of 3 years practical hands-on experience with analog layout tools/physical design/mask layout required. CAD experience with setting up Analog layout tools and flow is desirable and experience with advanced node physical design would be a plus. Responsibilities will

Cadence Design Systems is looking for a candidate to be part of its Technical Field Organization in the Silicon Package Board group, with a focus on PCB design solutions. If you like to develop solutions for challenging problems at top tier customers in an innovative and fast paced environment, using state of the art technology, this is a great opportunity.

As an Application Engineer you will have the exciting opportunity to work closely with customers supporting technical campaigns by delivering product demonstrations, knowledge transfer, training and onsite support. This will involve working with packaging of electronics using highly integrated IC package co-design and multi-die chiplet methodologies. The candidate should have knowledge of standard IC packaging methods including wirebond, flipchip ,

Description : Execute and deliver on EM/IR analysis & IR aware ECO flows and ensure integrity of delivered solutions. Support customer design teams for Voltus solutions/bug fixes Define and refine the methodologies /flows for gate-level and transistor level designs. Efficiently translate customer requirements into tool solutions by working closely with R&D Explore and define new in-design flows  by working with

Cadence place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis) and experience are required. Design experience should include ASIC design using industry-standard hardware description languages (Verilog/SystemVerilog) Demonstrated skills at understanding customer needs and identifying solutions to their challenges with Cadence digital design tools Exposure to digital IC design and experience in applying solutions in the RTL-GDSII digital

Position responsibilities include: Drive key customer engagements in cooperation with local/international Field Applications team Interface with R&D team to drive and influence product development to fulfill customer requirements Manage beta programs, author documentation and track customer issues Travel, including international travel, may be required Position requirements: Candidate must have 8+ years relevant industry experience with a MSEE -or- 12+ years experience with a BSEE Requires

We are looking for a design Verification expert with good subsystem and SOC level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Ability to coach and mentor less experience teammates. Should have worked on time-bounded projects leading to Si realization. Must be a US Citizen or Green Card holder for this position.​ Independently handle verification

As an integral part of the Cadence Education Services Team, you will create and deploy customer training for Cadence’s state-of-the-art tools, languages, and methodologies. The training content that you develop will be for the classroom, virtual, and online delivery. In this role, you will develop and update course lectures, labs, videos, and related collateral to enable our customers to become