Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this
R&D Engineer At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share
Analog/Mixed-Signal Layout Design Engineer II – DTE This is a Defined Term position for September 2021 to April 2022. In this role you will be responsible for designing physical layout of custom analog and digital blocks for multi-Gb/s SERDES IP. As mixed-signal layout engineer you will be exposed to SerDes PHY layout for PCIe, SATA, XAUI, and other protocols. As a
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
In this role you will be leading and overseeing the activities of a talented team, responsible for project Management of mixed-signal IP projects. The successful candidate will work on a variety of management tasks both at Project and Program level and will also be directly involved on driving standardization flows/processes related with Project Management. Specific responsibilities will include driving initiatives,
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