Analog/Mixed-Signal Layout Design Engineer II – DTE
This is a Defined Term position for September 2021 to April 2022. In this role you will be responsible for designing physical layout of custom analog and digital blocks for multi-Gb/s SERDES IP. As mixed-signal layout engineer you will be exposed to SerDes PHY layout for PCIe, SATA, XAUI, and other protocols. As a designer of IP layout, circuits will be constructed so as to facilitate porting to multiple process nodes. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
Requirements
- BSEE plus a minimum of 2 years in the following areas:
- In depth familiarity with layout of analog and mixed signal CMOS circuits
- Exposure to SERDES subcircuit layout (ie. RX, TX, PLL, etc…)
- Knowledge of signal integrity issues (ie. clock/data routes, differential routing, shielding)
- Aware of layout techniques to mitigate ESD, latchup
- Familiarity with custom digital layout (ie. high speed logic paths)
- Knowledge of design for reliability (ie. EM, IR, etc…)
- Knowledge of layout effects (ie. matching, reliability, proximity effects, etc…)
- Good understanding of how layout tools function and have had experience using them.
- Verification tools: Hercules, ICV, Star-RCXT
Nice to have:
- Design for porting experience (ie. design so as to enable ease moving layout across multiple foundry nodes)
- Exposure to scripting (ie. TCL, PERL, etc…)
