At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This R&D engineer role is part of the timing optimization group of Cadence’s Innovus Place & Route product. This key Innovus R&D group is responsible for optimizing timing (how fast a chip functions) and power (the power consumption of the chip), and the timing closure flow. The Innovus product is a key product used by a variety of chip manufacturing companies such as mobile, automotive, CPU & GPU cores, & AI. The work done in this high-performance team has a huge impact on the chip industry and products that are used in our daily lives.
We are looking for talented candidates with a strong background in electronic design automation (timing, power analysis, optimization), and excellent software engineering skills, experience with multithreaded and distributed optimization. We are looking for individuals that can make the next breakthrough in the technology that we provide to the customers, making a big impact to the industry.
Minimum Qualifications:
Highly technical engineer with excellent problem solving skills
C/C++ software development experience in Linux environment
Strong understanding and extensive usage of data structures and algorithms
Great communication skills and a strong desire for working with customers
MS (Ph.D. track a plus) in Electrical Engineering, Computer Science.
Preferred:
Knowledge of physical synthesis algorithms, timing analysis and multithreading is a strong plus.
Prior R&D experience working on IC physical designs tools
Hands on experience using the above physical design tools for design closure and knowledge of physical design flows a plus.
Experience with Tcl and other scripting languages
