Principal Design Engineer

Cadence Design Full Time India Engineering

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description :

 

Be part of the Cadence DDR PHY IP development team responsible for –

 

-Defining microarchitecture of digital blocks to meet specifications, ensuring modularity , optimized for performance metrics of timing, area and power.

 

-Lead and also hands on RTL implementation and design processes of Lint/CDC/SDC definition/STA/Synthesis.

 

-Collaborate with cross functional teams of Architecture, Verification , Physical Design and Mixed Signal teams , ensure alignment of requirements and driving resolution of issues.

 

-Mentor junior members of the team.

 

-Provide technical assistance to customer support team.

 

Requirements :

 

B.E/M.Tech in Electronics Engineering.

 

8+ years of relevant experience in Digital Design.

 

Hands on experience in micro-architecting digital blocks and RTL implementation.

 

Hands on experience in SDC definition, STA , Lint Checks, CDC and Synthesis.

 

Prior experience of working on any of the memory subsystem blocks is highly desirable but not a must.

 

We’re doing work that matters. Help us solve what others can’t.

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