Principal Solutions Engineer – AE

Cadence Design Full Time India Engineering

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

Design Verification expert with good subsystem and IP level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Independently handle verification of subsystem/IP. Define methodology for subsystem/IP verification. Follow systematic approach of metric driven verification with meticulous attention to quality and completeness. Should be able work closely across teams to meet delivery timelines.

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