Sr Principal Product Engineer

Cadence Design Full Time India Engineering

Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Requirements

 

STA engineer must have worked in defining STA constraint by interacting with functional, DFT , PnR teams .

Must have very good clarity on corners & various margins (derate, uncertainty, jitter, ID drop etc) need in flow.

Must have understanding of low power architecture like need for power domains ,UPF, CPU CPF specification etc. & their relevance in STA flows.

Must have worked on critical timing ECO & power closure (ECO), Metal ECO for signoff at SOC level.

Good understanding of scripting language like TCL , perl and shell.

Problem Solving attitude – ability to Identify complex problems and review related information to develop and evaluate options and implement solutions.

Good team player, have passion on driving engagements of your own.

We’re doing work that matters. Help us solve what others can’t

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